Server name: xeon.ucdenver.pvt
Overview
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Intel Xeon Phi coprocessors have been designed by Intel Corporation as a supplement to the Intel Xeon processor family. These computing accelerators feature the MIC (Many Integrated Core) architecture, which enables fast and energy-efficient execution of High Performance Computing (HPC) applications utilizing massive thread parallelism, vector arithmetics and streamlined memory access. The term “Many Integrated Core” serves to distinguish the Intel Xeon Phi product family from the “Multi-Core” family of Intel Xeon processors.
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An Intel Xeon Phi coprocessor
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That processor family uses the Intel Hyper-Threading Technology (Intel HT Technology), which was developed by Intel in order to improve the performance of IA-32 processors when executing multi-threaded operating system and application code or single-threaded applications under multi-tasking environments. The technology enables a single physical processor to execute two or more separate code streams (threads) concurrently using shared execution resources.
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Intel Xeon Processor E5-2600v2 Architecture
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Hardware Components
Intel Xeon Processor
There are 2 Intel Xeon Processors installed in the PDS Lab, each of them has the following configuration:
| Model |
Intel(R) Xeon(R) CPU E5-2650 v2 @ 2.60GHz |
| CPU MHZ |
1200.000 |
| CPU cores per Processor |
8 |
| Thread(s) per core |
2 |
| Total of threads per processor |
16 |
| Host physical memory |
65933 MB |
| Architecture |
x86_64 |
| CPU op-mode(s) |
32-bit, 64-bit |
| Byte order |
Little Endian |
| Host OS |
Linux |
| OS version |
2.6.32-431.el6.x86_64 |
| L1 dcache |
32 KB |
| L1 icache |
32 KB |
| L2 cache |
256 KB |
| L3 cache |
20480 KB |
| Cache alignment |
64 |
| Address sizes |
46 bits physical, 48 bits virtual |
| NUMA node(s) |
2 |
| NUMA node0 CPU(s) |
0-7, 16-23 |
| NUMA node1 CPU(s) |
8-15, 24-31 |
| OS |
CentOS Linux release 7.2.151 (64bits) |
| Management |
IPMI 2.0 & KVM with Dedicated LAN - Integrated |
Xeon Phi Coprocessor
There are two Intel Xeon PHI Co-processors installed in the PDS Lab. These two co-processors are called mic0 and mic1, and each of them has the following configuration:
Device No: 0, Device Name: mic0
| Device Series |
Intel(R) Xeon Phi(TM) coprocessor 7120P |
| Number of cores |
61 |
| Threads per core (Hyper Threads) |
4 |
| Total of threads |
244 |
| Frequency |
57 to 61 cores at ≈1 GHz |
| uOS Version |
2.6.38.8 + mpss3.3 |
Device No: 1, Device Name: mic1
| Device series: |
Intel(R) Xeon Phi(TM) coprocessor 7120P |
| Number of cores: |
61 |
| Threads per core (Hyper Threads) |
4 |
| Total of threads |
244 |
| Frequency |
57 to 61 cores at ≈1 GHz |
| uOS Version |
2.6.38.8 + mpss3.3 |
GDDR
| GDDR Vendor |
Samsung |
| GDDR Version |
0x6 |
| GDDR Density |
4096 Mb |
| GDDR Size |
15872 MB |
| GDDR Technology |
GDDR5 |
| GDDR Speed |
5.5 GT/s |
| GDDR Frequency |
2750000 kHz |
| GDDR Voltage |
15010000 uV |
