Systems Lab - PDS Lab
Department of Computer Science and Engineering
College of Engineering and Applied Science
University of Colorado at Denver
This webpage has all the information needed for
the students to develop their labs in the Parallel and Distributed Processing
(CSCI 5551/7551) and the Advanced Computer Architecture (CSCI 5593) courses.
The official PDS Lab website is located at http://pds.ucdenver.edu/ , which
provides information about the lab, equipment, facilities, software and
hardware documentations, activities, etc.
the PDS Lab we currently have three machines providing a variety of
a 192 core cluster consisting of 16 AMD Opteron 2427 nodes (12 core each), with
8 Tesla Fermi GPUs on connected to computer nodes (0, 1, 12, 13);
an AMD 64 core machine with an NVIDIA Kepler GPU (K40c);
and Xeon-Phi, Intel multicore machine with Phi coprocessors.
- Heracles, a Microway Xeon 1U Cluster with 18 nodes and 4 Tesla P100 GPUs.
you obtain an account, you may logon to the PDS Lab system. Upon approval of
your request for an account, an email will be sent to you with your account
information. Users are welcomed to come to the lab room to work on the Hydra,
Xeon or Dozer or can remotely connect to them from their personal computers.
- hydra.ucdenver.pvt, for accessing Hydra cluster.
for accessing Dozer machine.
- xeon.ucdenver.pvt, for accessing Xeon, Intel multicore
link below gives you the information you need to configure your personal
computer to access the PDS lab machines:
- heracles.ucdenver.pvt for accessing Heracles cluster.
- Heracles - Multicore Cluster
- Running MPI programs on Heracles
- Hydra - Multicore Cluster
- Intel Xeon and Phi - Processor and Coprocessor
Compiling Sequential Programs on Heracles, Hydra
Compiling Sequential Programs on Xeon and Heracles by using Intel Compilers
Compiling Parallel Programs (OpenMP and Cuda) on Heracles, Hydra and
Compiling MPI Programs on Hydra
Compiling Parallel Programs openMP on Xeon by using Intel Compilers
jobs on the servers
Profiling CUDA applications
- Instruction Trace: Link
Instruction trace can be used for projects related branch predictions/analysis. You can find in reference link the description of
raw trace files all from SPEC benchmarks.
Note that you may need to use parser provided, or your own parser to extrace information you
need for your projects.
- Cache Simuluation Trace:
The trace file go_ld_trace.zip containes a trace of load instructions executed for some programs. Each line
represents a Byte address referenced by executed load instruction.
To help compress the file, instead of storing the abosulute address, the
difference from the last address in the trace are store. You need to restore the absolute memory address before using the trace for your cache simulator.
An example of code reading the traces here: read_ld_trace.c.
- Other useful links:
- Generate memory trace tools for cache simulation
- Cache simulator