Xeon and Phi Architectures

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Xeon Multi-core Machine

The Xeon architecture in our lab consists of following components:

                                Figure 1 - Xeon-Phi Architecture

Intel Xeon Processor


Figure 2 - ntel Xeon E5-2650v2 Architecture

There are 2 Intel Xeon Processors installed in the PDS Lab, each of them has the following configuration:

Processor
 Intel(R) Xeon(R) CPU E5-2650 v2 @ 2.60GHz
Operationg System
 CentOS Linux release 7.2.1511
CPU cores per Processor
 8
Thread(s) per core
 2
Total of threads per Processor
16
Host Physical Memory
 64229 MB
CPU op-mode(s)
 32-bit, 64-bit
Host Physical Memory
 65933 MB
L1 dcache
 32K
L1 icache
 32K
L2 cache
 256K
L3 cache
 20480K
cache_alignment
 64
address sizes
 46 bits physical, 48 bits virtual

Intel Phi Coprocessor



                                     Figure 2 - Phi microarchitecture

The Intel Xeon Phi coprocessor is primarily composed of processing cores, caches, memory controllers, PCIe client logic, and a very high bandwidth, bidirectional ring interconnect (Figure 2). Each core comes complete with a private L2 cache that is kept fully coherent by a global-distributed tag directory. The memory controllers and the PCIe client logic provide a direct interface to the GDDR5 memory on the coprocessor and the PCIe bus, respectively. All these components are connected together by the ring interconnect.

There are two Intel Xeon PHI Co-processors installed in the PDS Lab. These two co-processors are called mic0 and mic1, and each of them has the following configuration:

Device Series
 Intel Xeon Phi Coprocessor 7120P 16GB 1.238GHz 61 cores 300W
Number of Cores
 61
Threads per core (Hyper threads)
 4
Total of Threads
244
Frequency
1,24 GHz
Coprocessor OS Version
 2.6.38.8+mpss3.7.1


Monitoring Phi Coprocesors


Use the command

micsmc

a utility for monitoring the physical parameters of Intel Xeon Phi coprocessors: model, memory, core rail temperatures, core frequency, power usage, etc.,